Electrostatic discharge (ESD) events can cause damage to elements of circuitry due to current overload or reverse biasing. For example, the propagation of an ESD event through a circuit may cause a transistor to greatly exceed its current capacity, suffer physical damage, and subsequently fail. The potential for failure increases as circuitry becomes smaller and as voltage levels are reduced. ESD events may occur due to a relatively short period of high voltage or current imposed on a device. For example, ESD events are sometimes caused by contact with a human body, by machinery such as manufacturing or test equipment, or in electrically noisy environments, as may be incurred in many applications. A variety of ESD events can occur in electronic devices, including discharge between the pads of an integrated circuit, discharge between voltage supply terminals, and discharge between pads and voltage supply terminals. Various ESD protection circuitry is used in the arts to protect ICs from damage due to the occurrence of ESD events during manufacture, testing, and operation. In general, ESD protection circuitry is designed to protect the input/output pins or terminals and thereby shield the internal circuitry of an integrated circuit from excessively large and sudden discharges of electrostatic energy. Each pin in an integrated circuit must be coupled to an appropriate ESD protection circuit such that the ESD discharge current is shunted away from the internal portions of the chip that are the most sensitive to damage. As such, ESD discharge paths are often provided between every pair of pins in an IC for both positive and negative polarities.
ESD discharges are brief transient events that are usually less than one microsecond in duration and much higher in voltage than the normal operating voltage range. Furthermore, the rise times associated with these brief pulses are usually less than approximately twenty nanoseconds. The ESD protection circuit must begin conducting almost instantaneously so as to shunt the resulting ESD current. However, the ESD protection circuit must not respond to smaller voltage increases such as normal power-up events in usual chip operation. If the ESD protection circuit were to trigger erroneously and conduct during normal operation, the desired functioning of the IC could be compromised. Furthermore, in addition to triggering when needed for ESD protection, the ESD protection circuit must stay in a highly conductive state for the duration of the ESD pulse so that all of the ESD energy is safely discharged. If the ESD protection circuit were to shut down prematurely, damaging potentials could build up quickly and cause device failure. Yet another conflicting demand on an ESD protection circuit, however, is the need to shut down when ESD protection is no longer needed following an ESD event. Many ESD protection cells known in the art have a tendency to latch-up in an “on” state after an ESD event. One skilled in the arts is required to balance the tradeoffs among factors including ESD protection, resistance, and chip area constraints.
It is known to use silicon controlled rectifier (SCR) ESD protection cells in some applications, primarily due to economies in die area. One problem with SCRs that prevents their more widespread use, is that they have a tendency to latch up when exposed to fast transients, sometimes called “rate firing”. As a result, an SCR ESD protection cell can be triggered by fast transients rather than an ESD event, or may remain in an “on” state beyond the duration of a triggering ESD event. Spurious triggering is obviously not helpful in providing ESD protection and latch-up is undesirable from a power consumption standpoint, as the latched ESD protection cell is permitted to draw supply current during periods when ESD protection is not required. Another problem encountered when using SCR circuits for ESD protection is directionality. Since common SCR circuits operate responsive to either a negative or positive voltage, it is known in the arts to use opposing SCR ESD protection circuits in pairs for bidirectional applications. A floating N-well is usually used in such instances to separate the individual SCRs, this makes the SCR pairs more susceptible to rate firing. Thus, although SCR circuits are sometimes used for protecting associated circuitry from damage due to ESD over-voltage stress, quiescent current consumption is higher, and die area is larger, than it might otherwise be.
Due to these and other problems, a need exists for circuits and methods that provide microelectronic circuits with SCR ESD protection having reduced area and low leakage, without adversely impacting the performance of the functional circuit path during normal operation.